Since signal reflection errors are increased with the development of ultrahigh speed synchronous semiconductor memory devices, it becomes more important to match the impedance of interface circuits, such as data driver circuits, with the impedances of the signal lines of a bus in order to prevent reflection errors during the transferring of high frequency signals. When designing a printed circuit board (PCB), discrete resistors (or external resistors) are also provided, corresponding to the impedances of the signal lines of the bus connected to the semiconductor memory device. In this way, the impedance of the interface circuit of the device is automatically matched with the impedances of the bus according to the values of the discrete resistors. To this end, an impedance adjustment circuit is provided in the ultrahigh speed synchronous device.
FIG. 1 shows the (V.sub.DS -I.sub.DS) relationship of a MOS transistor, and FIG. 2 the variation of the operating point of the MOS transistor with the resistor values corresponding to the impedances of the bus. When designing the PCB, it must be determined whether the impedances of the signal lines of the bus are matched with the impedances of the respective data driver circuits. In other words, the impedance of each data driver circuit is measured under the designing voltage, e. g., V.sub.DD /2. In this case, the on-resistance of the MOS transistor constituting the data driver circuit is determined at the operating point of V.sub.DD /2, as shown in FIG. 1, where V.sub.DD /2 represents the power source of the data driver circuit.
The impedance adjustment circuit has a transistor array consisting of MOS transistors to adjust the impedance of the data driver circuit. As the value of the discrete resistor connected to the impedance adjustment circuit varies, the operating point of the MOS transistors of the transistor array change their position from "b" (V.sub.DD /2) to either "a" or "c". Hence, while the impedance of the data driver circuit is determined under a designing voltage (V.sub.DD /2), the impedance of the transistor array is determined under the different voltages ("a" or "c"). This may cause the impedance of the data driver circuit determined by the impedance adjustment circuit to differ from the signal impedance of the bus, thereby increasing the transmitted signal reflection.